About the Role
• Research and develop novel computer architectures (e.g., CPU/NPU/GPU/TPU cores, domain-specific accelerators, memory hierarchies, emerging interconnect technologies) to address
cutting-edge compute challenges.
Responsibilities
• Design, model, and optimize methodologies for high-performance logic synthesis, physical
design, verification, and AI-driven design-space exploration.
• Develop libraries for software-hardware co-design and system-level optimization.
• Work with architecture, software, ASIC, and circuit design teams to define microarchitecture
(e.g., memory systems, interconnects) and translate research insights into scalable silicon
solutions.
• Define and implement coverage strategies, verification plans, and functional validation at
multiple levels (RTL, system).
• Perform trade-off analysis of hardware implementations for performance, power, and area
(PPA).
• Publish research in top-tier conferences (e.g., ISCA, MICRO, DAC) and contribute to patent
filings.

Qualifications
• Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Required Skills
• Solid understanding of computer system architecture (including aspects like super-scalar and
out-of-order execution), multi-core/AI-core architectures, cache coherency, and emerging
paradigms (e.g., neuromorphic/quantum systems).
• Proficiency in tools/methods for logic synthesis, physical design, formal verification, DFT, or AI-driven optimization (e.g., ML for placement & routing).
• Advanced C++/Python; familiarity with SystemC, TCL, AArch64 assembly, or ML frameworks
(PyTorch/TensorFlow) is a plus.
• Experience with RTL design (Verilog/System Verilog), architecture simulators (Gem5, SST), and
ASIC toolchains.

Preferred Skills
• Low-power/high-speed circuit design, complex RTL module development, or AI-driven
architecture exploration will be bonus skills.