Responsibilities
• Design, model, and evaluate high-performance Analog IPs (e.g., SERDES, PLLs, LDOs, DC/DC
converters, amplifiers, bandgap references) and DDR/LPDDR I/O interfaces across feasibility,
benchmarking, and micro-architecture definition phases.
• Perform transistor-level and system-level simulations (HSPICE, Spectre) to optimize
performance, power, and area (PPA) for analog circuits.
• Work on analog IC design such as Amplifier, Bandgap, DC/DC, AC/DC, LDO and etc.
• Work on IC reliability design (e.g. chip-level ESD, system-level ESD, Latch-up, Surge and etc).
• Guide physical design engineer to complete layout floorplan and physical design.
• Responsible for transistor-level and system-level design and simulation.
• Help test engineer to complete evaluation of IC or test chip and sample delivery.
• Guide test engineer to complete chip level ESD/Latch-up and system level ESD/Surge test
evaluation plan.
• Explore emerging analog circuit techniques and DDR interface architectures to address next-generation compute and memory challenges.

Qualifications
• Ph.D. in Electrical Engineering, Microelectronics, or a related field.

Required Skills
• Solid experience in analog/mixed-signal IC design (e.g., amplifiers, LDOs, PLLs, bandgap
references) and familiar with design tools (HSPICE, Spectre, Cadence).
• Experience with DDR I/O circuit design, high-speed SERDES, or memory interface architectures
(preferred).
• Knowledge of layout optimization for analog circuits (e.g., matching, parasitics, noise isolation).
• Collaborative team player with strong problem-solving skills and attention to detail.