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Power Factor Correction Circuit for a Power Electronic System

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Opportunity 

Power electronic systems, such as those used in computers, mobile devices, and industrial equipment, often rely on switching converters to adjust voltage levels for different operational requirements. However, these converters introduce significant challenges, including reduced power factor (PF) and high harmonic distortion in the input current. The power factor is a measure of how effectively electrical power is converted into useful work, and a low PF indicates inefficiency. Harmonic distortion, caused by the non-linear switching of converters, pollutes the power grid, leading to energy losses and potential damage to other connected devices. Traditional solutions, such as passive LC filters or interleaved boost converters, are either bulky or fail to fully eliminate ripple currents, especially in discontinuous conduction mode (DCM). This creates a demand for a compact, efficient, and high-performance power factor correction (PFC) circuit that can seamlessly integrate into modern power electronic systems without compromising power density or efficiency. 

Technology  

The patent introduces a semiconductor-based power factor correction circuit that addresses the limitations of traditional PFC methods. The core innovation lies in the use of a series-pass device (SPD), typically a bipolar junction transistor (BJT), connected in series with the power converter. The SPD actively controls the input current waveform, ensuring it aligns with the input voltage waveform to achieve near-unity power factor. A dual-loop feedback mechanism regulates the SPD’s operation:  

  1. "i-control" loop: Compares the output voltage with a reference and adjusts the input current to match a sinusoidal reference derived from the input voltage.  
  2. "v-control" loop: Maintains the voltage across the SPD at a minimal level (slightly above its saturation voltage) to minimize power dissipation.  

The system also includes a small film capacitor to absorb high-frequency noise, eliminating the need for large passive filters. This approach not only improves PF and reduces total harmonic distortion (THD) but also enhances power density by replacing bulky components with a compact semiconductor solution.

Advantages 

  • High Power Factor (PF): Achieves PF > 0.995 across varying loads.  
  • Low Harmonic Distortion: THD as low as 1.48% at 150 W output.  
  • Compact Design: Replaces large passive filters with a semiconductor-based circuit, reducing size and weight.  
  • High Efficiency: Operates at 94.3%–96.8% efficiency across 50–150 W loads.  
  • Fast Transient Response: Maintains stable output voltage (±50 V) during load changes.  
  • Monolithic Integration Potential: Can be packaged as an integrated circuit (IC) for higher power density.  

Applications

  • Consumer Electronics: Power supplies for laptops, smartphones, and TVs.  
  • Industrial Equipment: Motor drives, uninterruptible power supplies (UPS), and renewable energy systems.  
  • Electric Vehicles (EVs): On-board chargers and DC-DC converters.  
  • LED Lighting: High-efficiency drivers with low THD.  
  • Data Centers: Server power distribution units (PDUs).
Remarks
IDF: 367
IP Status
Patent granted
Technology Readiness Level (TRL)
4
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Power Factor Correction Circuit for a Power Electronic System

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